1. Field of the Invention
The present invention relates to semiconductor nonvolatile memory, which utilizes floating gates, and more particularly to semiconductor nonvolatile memory, which eliminates delay in erase operation and reduces stress on a tunnel dielectric layer.
2. Description of the Related Art
A semiconductor nonvolatile memory, which makes use of floating gates, is electrically rewritable, can retain data even in the power OFF state, and is widely used as flash memory.
FIG. 1 is a diagram showing the cell structure of a conventional semiconductor nonvolatile memory. FIG. 1A is an erase state, in which data xe2x80x9c0xe2x80x9d is stored. FIG. 1B is a programmed state (written state), in which data xe2x80x9c1xe2x80x9d is stored. As for the cell structure, an n-type source region 11 and drain region 12 are formed at the surface of a p-type semiconductor substrate 10, a floating gate FG is formed via a tunnel dielectric layer (normally an oxide layer) above the channel region therebetween, and, in addition, a control gate CG is formed via a dielectric layer thereabove.
When a charge, such as electrons, is not stored in a floating gate FG, it is an erased state, in which the threshold voltage of a cell transistor is low, and data xe2x80x9c0xe2x80x9d is stored. In this state, when a prescribed read-out voltage is applied to the control gate CG, the cell transistor conducts. Conversely, when a charge, such as electrons, is stored in the floating gate FG, it is a programmed state, in which the threshold voltage of a cell transistor is high, and data xe2x80x9c1xe2x80x9d is stored. In this state, even if a read-out voltage is applied to the control gate CG, the cell transistor does not conduct. Data determination is performed in accordance with a cell current, which is generated by the conduction and non-conduction of the cell transistor. Furthermore, for the sake of brevity, examples will be explained hereinbelow using electrons as the charge stored on a floating gate.
The writing (programming) and erasing of data are performed by injecting and extracting electrons into and from a floating gate FG via a tunnel dielectric layer 13. In a write operation (programming operation), for a cell in an erased state, hot electrons are generated in the channel region by applying 10 V, for example, to the control gate CG, 5 V, for example, to the drain 12, and 0 V, for example, to the source 11, and the hot electrons thereof are injected into the floating gate FG by an electric field resulting from the positive voltage applied to the control gate CG. Determining whether or not write is complete is performed by applying a prescribed program verify voltage to the control gate, and checking cell current in accordance with the conduction, non-conduction of the cell transistor.
In an erase operation, for a cell in a programmed state, xe2x88x9210 V, for example, is applied to the control gate CG, the drain 12 is set to the floating state, and 5 V, for example, is applied to the source 11 as well. In accordance therewith, a high electric field is generated in the tunnel dielectric layer 13, and electrons in the floating gate FG tunnel through the tunnel dielectric layer 13 by the FN (Fowler-Nordheim) tunneling effect, and are extracted to the source 11. Determining whether or not erase is complete is-performed by applying a prescribed erase verify voltage to the control gate, and checking cell current in accordance with the conduction, non-conduction of the cell transistor.
An erase operation is generally not performed in memory cell units, but rather, is performed collectively in either block units or chip units comprising a plurality of memory cells. Thus, in an erase operation, all cells are initially set to the written state (programmed state). Thereafter, the above-mentioned erase operation is performed for all memory cells. Further, an erase operation is performed while carrying out erase verify each time an erase pulse is applied.
A read-out operation is performed by applying 5 V, for example, to the control gate of a selected memory cell, 1 V, for example, to the drain, and 0 V, for example, to the source, and checking the conduction/non-conduction of the cell transistor. As for the voltage applied to the control gate, an intermediate value of the threshold voltages of the erased state and programmed state (written state) is selected.
In the above-mentioned erase operation, a large number of electrons remain on a floating gate at the start of erase operation. Therefore, when xe2x88x9210 V is applied to the control gate, the potential resulting from the electrons on the floating gate is increased, and an excessive electric field is applied to the tunnel dielectric layer 13. When the electric field across the tunnel dielectric layer 13 is high, tunnel current becomes larger, and erase time becomes shorter, but a high electric field places excessive stress on a tunnel dielectric layer, causing damage and bringing about degradation or destruction. Therefore, there is a limit for high electric field to be placed on a tunnel dielectric layer.
Accordingly, in the past, there was proposed a variable erase voltage system, in which the voltage applied to a control gate during an erase operation is set low at the initial stage of erase, and is increased in line with the progress of the erase operation. According to this system, for example, a voltage of approximately xe2x88x926 V is applied to the control gate at the start of erase operation, and as erasure progresses, the control gate voltage is lowered to xe2x88x9210 V. In this manner, the electric field being applied to the tunnel dielectric layer can be maintained constant to a certain degree, making it possible to prevent the applying of an excessive electric field to the tunnel dielectric layer, and to curb the degradation or destruction of the tunnel dielectric layer.
However, a conventional variable erase voltage system uniformly changes the erase voltage applied between a control gate and a substrate in accordance with erase time, or more specifically, with the number of erase pulses. For example, at the stage of designing a memory, an optimum erase voltage rise curve is determined for a number of erase pulses, and the erase voltage rise curve thereof is applied to all memory devices. As a result thereof, when erase speed differs from the design value due to production irregularities, either the electric field applied to the tunnel dielectric layer is too low and erase time becomes prolonged, or the applied electric field is too high and causes the degradation of the tunnel dielectric layer.
For example, as a typical example of a production irregularity, there is the variation in the thickness of a tunnel dielectric layer. When a tunnel dielectric layer becomes thick, the erase speed for the same control gate voltage slows down. In the case thereof, until the erase voltage is increased after a certain amount of erase time has elapsed, and, consequently, the electric field applied to the tunnel dielectric layer becomes higher, not much erasing is done, and actual erase time becomes longer than the set erase time.
By contrast, when a tunnel dielectric layer becomes thin, the erase speed for the same control gate voltage increases. In this case, because an excessive electric field is continuously applied to the tunnel dielectric layer, the degradation of the tunnel dielectric layer occurs. In particular, when the erase voltage is uniformly raised in accordance with erase time, such an excessive electric field becomes even more prominent.
Accordingly, an object of the present invention is to provide an optimum variable erase voltage system for a memory for which erase speed fluctuates in accordance with production irregularities.
Further, another object of the present invention is to provide a semiconductor nonvolatile memory for optimally controlling changes in erase voltage corresponding to changes in erase speed resulting from production irregularities.
To achieve the above-mentioned objects, the present invention provides a semiconductor nonvolatile memory provided with a plurality of memory cells having floating gates, which enables an optimum erase operation, even when the erase rate fluctuates due to production irregularities, by monitoring the state of a memory cell during erase process and controlling the erase voltage applied to a control gate in accordance with the state of erase progress. As a specific example of the state of a memory cell, which is monitored during erase process, leakage current of a memory cell during erase process is monitored.
For example, a portion or all of the memory cells being erased are selected, and the drain current (cell leakage current hereinbelow) is checked when a prescribed voltage is applied to the control gates. In a state where erase is not being adequately performed due to numerous electrons remaining on a floating gate, the cell leakage current is small. Conversely, because the electrons on a floating gate decrease in line with erase progress, the cell leakage current becomes large. Therefore, when the cell leakage current is small, since a large number of electrons remain on a floating gate, the erase voltage applied to a cell is reduced to suppress the electric field of a tunnel dielectric layer. By contrast, when the cell leakage current is large, since a small number of electrons remain on a floating gate, the erase voltage is increased so as to make it possible to achieve highspeed erase. An excessive electric field is not generated inside a tunnel dielectric layer even if the erase voltage is increased.
According to the above-mentioned invention, because the erase progress state of a cell is detected via cell leakage current, and erase voltage is controlled to be changed from a low level to a high level in accordance therewith, therefore, even if the erase speed fluctuates due to production irregularities, it is possible to prevent the prolonging of erase time, while avoiding the application of an excessive electric field to a tunnel dielectric layer, making it possible to guarantee an optimum erase operation.
To achieve the above-mentioned objects, a first aspect of the present invention is a semiconductor nonvolatile memory, comprising a plurality of memory cells, which are provided with floating gates above a semiconductor substrate with a tunnel dielectric layer interposed therebetween, and which also have control gates; and an erase control circuit which detects cell leakage current by applying a leakage detecting voltage to the control gate of a memory cell to be erased, and gradually increases an erase voltage applied between the control gate and the semiconductor substrate in accordance with the detected cell leakage current.
In the first aspect of the above-mentioned invention, for a first embodiment, the erase control circuit controls the erase voltage to a first voltage when the cell leakage current is a first leakage current, and controls the erase voltage to a second voltage larger than the first voltage, when the cell leakage current is a second leakage current larger than the first leakage current.
Furthermore, in the first aspect of the above-mentioned invention, for another embodiment, when the cell leakage current is lower than a reference value which rises in accordance with erase time, the erase control circuit induces the erase voltage higher in accordance with the erase time, and when the cell leakage current is higher than the reference value, induces the erase voltage lower in accordance with the erase time.
To achieve the above-mentioned objects, a second aspect of the present invention is a semiconductor nonvolatile memory, comprising a plurality of memory cells, which are provided with floating gates above a semiconductor substrate with a tunnel dielectric layer interposed therebetween, and which also have control gates; and an erase control circuit which detects cell leakage current by applying a leakage detecting voltage to the control gate of a memory cell to be erased, and controls a rise rate relative to erase time of an erase voltage applied between the control gate and semiconductor substrate in accordance with a change rate relative to the erase time of the detected cell leakage current.